The escalating requirements for high performance and density associated with ultra large scale integration semiconductor devices require high speed and reliability and increased manufacturing throughput for competitiveness. As gate lengths are reduced to increase the speed and density, problems such as short channel effects are encountered. For example. "punch through" arises when the drain voltage reaches a sufficient large value, and the depletion layer associated with the drain spreads across the substrate and reaches the source, thereby enabling the charge carriers in the drain region to punch through to the source. In addition, "hot carrier injection" arises when device dimensions are reduced but the supply voltage is maintained, thereby increasing the electric field generated in the silicon substrate. Such an increased electric field enables electrons in the channel region to gain sufficient energy to be injected onto the gate oxide, resulting in device degradation.
Various methods have been proposed to solve the short channel effects. According to the method disclosed in U.S. Pat. No. 5,602,045 by Kimura, shallow source/drain regions are formed within amorphous regions to suppress an increase of dislocated charge carriers at the interface between the amorphous region and substrate. As shown in FIG. 1, pocket regions 18 are formed in the surface portions of a p-well region 12 formed in the surface portion of a semiconductor substrate 10, by ion implanting a p type impurity, as shown by arrows A, employing gate oxide 16, gate electrode 17 and field oxide regions 14 as a mask. Then, lightly doped impurity layers 20 are formed within the confines of the pocket regions 18 by ion implanting an n type impurity, as shown by arrows B in FIG. 2.
After forming SiO.sub.2 sidewall spacers 30 on the side surfaces of the gate electrode 17 and gate oxide 16, as shown in FIG. 3, amorphous layers 32 are formed within the confines of the lightly doped impurity layers 20, by implanting ions with large mass numbers, e.g., Si, Ge, As, as shown by arrows C, employing the gate oxide 16, gate electrode 17, sidewall spacers 30 and field oxide 14 as a mask. The depth of amorphous layers 32 is determined to be greater than the depth of subsequently formed impurity layers 40. The amorphous layers 32 are formed while cooling the substrate 10 and well region 12 to reduce junction leak current from the impurity layers 40 to the well region 12.
As shown in FIG. 4, the impurity layers 40 are then formed by ion implanting an n type impurity, as shown by arrows D, to a depth smaller than that of the amorphous layer 32 even after a subsequent annealing step, thereby suppressing dislocated carrier charges at the interface between the amorphous layers 32 and the well region 12. As shown in FIG. 4, the resulting device comprises the shallow impurity layers 40 formed within the confines of the amorphous regions 32 which, in turn, are within the confines of the light doped impurity layers 20. Accordingly, the method disclosed in U.S. Pat. No. 5,602,045 forms the shallow impurity regions 40, obtaining reduced junction leakage. However, the amorphous layers 32. formed between the impurity regions 40 and lightly doped impurity layers 20, reduce the mobility of the carriers moving between the impurity regions 40 and lightly doped impurity layers 20, thereby reducing the device speed.
There is a need for efficient methodology for manufacturing a semiconductor device exhibiting improved short channel characteristics.